From 1733ea93c9e4157958ee7848c5758c117147af26 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 28 Apr 2019 19:57:41 -0500 Subject: Enable remaining I/O busses on Lattice control FPGA --- fpga/serial/lattice/eb85/main.v | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) (limited to 'fpga/serial/lattice/eb85/main.v') diff --git a/fpga/serial/lattice/eb85/main.v b/fpga/serial/lattice/eb85/main.v index 58c2a1e..ca07d59 100644 --- a/fpga/serial/lattice/eb85/main.v +++ b/fpga/serial/lattice/eb85/main.v @@ -17,6 +17,12 @@ module control_fpga_top output wire [3:0] four_bit_input, // Input to the user program from the remote access module input wire [7:0] eight_bit_output, // Output from the user program to the remote access module output wire [7:0] eight_bit_input, // Input to the user program from the remote access module + input wire [15:0] sixteen_bit_output, // Output from the user program to the remote access module + output wire [15:0] sixteen_bit_input, // Input to the user program from the remote access module + + input wire [5:0] lcd_data_in_address, + input wire [7:0] lcd_data_in_data, + input wire lcd_data_in_enable, input wire [7:0] led_segment_bus, input wire [3:0] led_digit_select, @@ -51,14 +57,6 @@ module control_fpga_top reg [7:0] diagnostic_led_data = 8'b0; - wire [15:0] sixteen_bit_output; // Output from the user program to the remote access module - wire [15:0] sixteen_bit_input; // Input to the user program from the remote access module - - wire [5:0] lcd_data_in_address; - wire [7:0] lcd_data_in_data; - wire lcd_data_in_enable; - - assign sixteen_bit_output = 16'b0; // Diable 16 bit input for now //assign led_bank = eight_bit_input; // Mirror input to the LEDs assign led_bank = diagnostic_led_data; // Show diagnostic data on LEDs @@ -84,10 +82,6 @@ module control_fpga_top end end - assign lcd_data_in_enable = 1'b0; // Disable LCD I/O for now - assign lcd_data_in_address = 6'b0; // Disable LCD I/O for now - assign lcd_data_in_data = 8'b0; // Disable LCD I/O for now - // Instantiate main remote access module remote_access #(RAM_ADDR_BITS) remote_access(.main_fifty_clock(main_50_mhz_clock), .user_logic_reset(guest_logic_reset), .remote_access_4_bit_output(four_bit_output), .remote_access_4_bit_input(four_bit_input), .remote_access_8_bit_output(eight_bit_output), -- cgit v1.2.1