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| author | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2013-03-13 23:11:33 -0500 |
|---|---|---|
| committer | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2013-03-13 23:11:33 -0500 |
| commit | 400d0abcff5986c764f4a25bec29c2af57286ee1 (patch) | |
| tree | 9781e87f719057ee73beeed575fadbe7bd8b2a94 /fpga/xilinx | |
| parent | 9d5b0368df03284bfef472acfd2bef2a1c8a26ff (diff) | |
| download | ulab-400d0abcff5986c764f4a25bec29c2af57286ee1.tar.gz ulab-400d0abcff5986c764f4a25bec29c2af57286ee1.zip | |
Avoid usage of TQTimer::singleShot in the FPGA viewer part
Repair "think-o" in the Spartan 6 block RAM HDL
Diffstat (limited to 'fpga/xilinx')
| -rw-r--r-- | fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v index c3e612c..f1d10be 100644 --- a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v +++ b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v @@ -14,7 +14,7 @@ module data_storage( output reg [7:0] douta); parameter RAM_WIDTH = 8; - parameter RAM_ADDR_BITS = 16384; + parameter RAM_ADDR_BITS = 14; // Xilinx specific directive (* RAM_STYLE="BLOCK" *) |