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author | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2013-10-30 02:28:57 -0500 |
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committer | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2013-10-30 12:13:17 -0500 |
commit | 8faa3da1094d1785d3343c2869d9f8c95f01cf97 (patch) | |
tree | d6a7e029810759972c17395a22593a75256f611c /fpga/xilinx | |
parent | b783a269490763ec242e967fa713dbf732e5ac13 (diff) | |
download | ulab-8faa3da1094d1785d3343c2869d9f8c95f01cf97.tar.gz ulab-8faa3da1094d1785d3343c2869d9f8c95f01cf97.zip |
Fix image distortion when certain greyscale values are utilized
Store last used values in FPGA viewer and programmer GUI for convenience on GUI restart
Diffstat (limited to 'fpga/xilinx')
-rw-r--r-- | fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v index f1d10be..60c1dff 100644 --- a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v +++ b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v @@ -13,20 +13,20 @@ module data_storage( input wea, output reg [7:0] douta); - parameter RAM_WIDTH = 8; - parameter RAM_ADDR_BITS = 14; - - // Xilinx specific directive - (* RAM_STYLE="BLOCK" *) - - reg [RAM_WIDTH-1:0] data_storage_ram [(2**RAM_ADDR_BITS)-1:0]; - - always @(posedge clka) begin - if (wea) begin + parameter RAM_ADDR_BITS = 14; + parameter RAM_WIDTH = 8; + + // Xilinx specific directive + (* RAM_STYLE="BLOCK" *) + + reg [RAM_WIDTH-1:0] data_storage_ram [(2**RAM_ADDR_BITS)-1:0]; + + always @(posedge clka) begin + if (wea) begin data_storage_ram[addra] <= dina; douta <= dina; - end else begin - douta <= data_storage_ram[addra]; + end else begin + douta <= data_storage_ram[addra]; end end |