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* First pass of logic analyzer functionality (GPMC interface and server)Timothy Pearson2014-02-271-1/+25
* Hard reset user device on connection and disconnection of FPGA viewerTimothy Pearson2014-01-131-1/+3
* Add initial version of a logic analyzer serverTimothy Pearson2014-01-121-3/+14
* Lower the uLab FPGA viewer GPMC clock to reduce errors on prototype lashupTimothy Pearson2014-01-101-5/+122
* Add initial GPMC test program and associated files for BeagleBone BlackTimothy Pearson2014-01-094-0/+442