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# This file is part of the Universal Laboratory (uLab)
#
# © 2017 - 2019 Raptor Engineering, LLC
# All Rights Reserved
#
# Licensed under the terms of the AGPL v3
MAX_FPGA_ROUTE_PASSES = 100
SOURCE_FILES = main.v remote_access.v
# Default seed
#ARACHNE_PNR_SEED = 1
# Selected seed from fastest placement search
# NOTE: Must be updated every time the Verilog source is modified, no matter how trivially!
# Does not need to be updated if firmware program (C) sources are modified
# 0 automatically uses the best placement result
ARACHNE_PNR_SEED = 0
#ARACHNE_PNR_SEED = 1
YOSYS_ICE40_SIM_LIB = $(shell yosys-config --datdir/ice40/cells_sim.v)
.PRECIOUS: control_fpga_%.int
control_fpga_%.tmg: control_fpga_%.int control_fpga.pcf
echo "Total path delay: inf ns (0.0 MHz)" > $@
-icetime -tmd hx8k -p control_fpga.pcf -P ct256 $< > $@ 2>&1
control_fpga_%.int: control_fpga.blif control_fpga.pcf
echo "" > $@
-arachne-pnr -s $* -d 8k -P ct256 -m $(MAX_FPGA_ROUTE_PASSES) -p control_fpga.pcf $< -o $@
control_fpga.int: control_fpga_1.tmg control_fpga_2.tmg control_fpga_3.tmg control_fpga_4.tmg control_fpga_5.tmg control_fpga_6.tmg control_fpga_7.tmg control_fpga_8.tmg control_fpga_9.tmg \
control_fpga_10.tmg control_fpga_11.tmg control_fpga_12.tmg control_fpga_13.tmg control_fpga_14.tmg control_fpga_15.tmg control_fpga_16.tmg control_fpga_17.tmg control_fpga_18.tmg control_fpga_19.tmg \
control_fpga_20.tmg control_fpga_21.tmg control_fpga_22.tmg control_fpga_23.tmg control_fpga_24.tmg control_fpga_25.tmg control_fpga_26.tmg control_fpga_27.tmg control_fpga_28.tmg control_fpga_29.tmg \
control_fpga_30.tmg control_fpga_31.tmg control_fpga_32.tmg control_fpga_33.tmg control_fpga_34.tmg control_fpga_35.tmg control_fpga_36.tmg control_fpga_37.tmg control_fpga_38.tmg control_fpga_39.tmg \
control_fpga_40.tmg control_fpga_41.tmg control_fpga_42.tmg control_fpga_43.tmg control_fpga_44.tmg control_fpga_45.tmg control_fpga_46.tmg control_fpga_47.tmg control_fpga_48.tmg control_fpga_49.tmg \
control_fpga_50.tmg control_fpga_51.tmg control_fpga_52.tmg control_fpga_53.tmg control_fpga_54.tmg control_fpga_55.tmg control_fpga_56.tmg control_fpga_57.tmg control_fpga_58.tmg control_fpga_59.tmg \
control_fpga_60.tmg control_fpga_61.tmg control_fpga_62.tmg control_fpga_63.tmg control_fpga_64.tmg
BEST_TRIAL=0; \
BEST_TRIAL_RESULT=0; \
for trial in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64; do \
CURRENT_TRIAL_RESULT=$$(cat control_fpga_$${trial}.tmg | grep "Total path delay" | awk '{print $$6}' | sed 's/(//g'); \
if [ "$$CURRENT_TRIAL_RESULT" != "" ]; then \
echo "control_fpga_$${trial}.tmg : $$CURRENT_TRIAL_RESULT"; \
COMPARISON_RESULT=$$(echo "$$CURRENT_TRIAL_RESULT > $$BEST_TRIAL_RESULT" | bc -l); \
if [ $$COMPARISON_RESULT -eq 1 ]; then \
BEST_TRIAL=control_fpga_$${trial}.tmg; \
BEST_TRIAL_RESULT=$$CURRENT_TRIAL_RESULT; \
fi; \
fi; \
done; \
if [ "$$BEST_TRIAL_RESULT" -eq "0" ]; then \
echo "Unable to determine fastest result. Selecting first run...."; \
BEST_TRIAL=control_fpga_1.tmg; \
BEST_TRIAL_RESULT=0; \
fi; \
echo "Fastest result: $$BEST_TRIAL : $$BEST_TRIAL_RESULT"; \
cp `echo $$BEST_TRIAL | sed 's/\.tmg/\.int/g'` control_fpga.int; \
cp $$BEST_TRIAL control_fpga.tmg
ifneq ($(ARACHNE_PNR_SEED),0)
cp control_fpga_$(ARACHNE_PNR_SEED).int control_fpga.int
cp control_fpga_$(ARACHNE_PNR_SEED).tmg control_fpga.tmg
endif
cat control_fpga.tmg
control_fpga.ex: control_fpga.int
icebox_explain control_fpga.int > control_fpga.ex
control_fpga.blif: $(SOURCE_FILES)
yosys -l yosys.log -q -p "synth_ice40 -top control_fpga_top -blif control_fpga.blif" $(SOURCE_FILES)
control_fpga.bin: control_fpga.int
icepack control_fpga.int control_fpga.bin
blank.rom:
dd if=/dev/zero ibs=1k count=256 | tr "\000" "\377" > blank.rom
control_fpga.rom: blank.rom control_fpga.bin
cp blank.rom control_fpga.rom
dd if=control_fpga.bin of=control_fpga.rom conv=notrunc
control_fpga_test.vcd: $(SOURCE_FILES) testbench.v
rm -f control_fpga_sim
rm -f control_fpga.vcd
/usr/bin/iverilog -DSIMULATION -o control_fpga_sim $(SOURCE_FILES) testbench.v
./control_fpga_sim
simulate: control_fpga_test.vcd
simulate_view: control_fpga_test.vcd
gtkwave control_fpga_test.vcd
all: control_fpga.rom
dump_toolchain_info:
-@echo "================================================================================"
-@echo "Base system:\t"
-@echo -n "Architecture:\t"
-@uname -m 2>/dev/null
-@echo -n "gcc:\t\t"
-@gcc -dumpversion 2>/dev/null
-@echo -n "clang:\t\t"
-@clang --version 2>/dev/null | head -n 1
-@echo "\nFPGA toolchain:"
-@echo -n "Icarus verilog:\t"
-@iverilog -V 2>/dev/null | head -n 1
-@echo -n "Yosys:\t\t"
-@yosys -V 2>/dev/null
-@echo -n "arachne-pnr:\t"
-@arachne-pnr -v 2>/dev/null
-@echo "================================================================================"
test: control_fpga.bin
iceprog -S control_fpga.bin
flash: control_fpga.bin
iceprog control_fpga.bin
clean:
rm -f control_fpga.blif control_fpga.ex control_fpga.int control_fpga.tmg control_fpga_*.int control_fpga_*.tmg control_fpga.bin yosys.log
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