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# This file is part of the Universal Laboratory (uLab)
#
# © 2017 - 2019 Raptor Engineering, LLC
# All Rights Reserved
#
# Licensed under the terms of the AGPL v3
# Main system clock
set_io main_12_mhz_clock J3
# Debug / GPIO connections
set_io led_bank[7] C3
set_io led_bank[6] B3
set_io led_bank[5] C4
set_io led_bank[4] C5
set_io led_bank[3] A1
set_io led_bank[2] A2
set_io led_bank[1] B4
set_io led_bank[0] B5
# Guest FPGA interface
set_io guest_logic_reset A16
set_io four_bit_output[3] C16
set_io four_bit_output[2] D16
set_io four_bit_output[1] E16
set_io four_bit_output[0] F16
set_io four_bit_input[3] B16
set_io four_bit_input[2] D14
set_io four_bit_input[1] D15
set_io four_bit_input[0] E14
set_io eight_bit_output[7] G16
set_io eight_bit_output[6] H16
set_io eight_bit_output[5] J15
set_io eight_bit_output[4] G14
set_io eight_bit_output[3] K14
set_io eight_bit_output[2] K15
set_io eight_bit_output[1] M16
set_io eight_bit_output[0] N16
set_io eight_bit_input[7] F15
set_io eight_bit_input[6] G15
set_io eight_bit_input[5] H14
set_io eight_bit_input[4] F14
set_io eight_bit_input[3] J14
set_io eight_bit_input[2] K16
set_io eight_bit_input[1] L16
set_io eight_bit_input[0] M15
set_io led_segment_bus[7] T1
set_io led_segment_bus[6] R2
set_io led_segment_bus[5] R3
set_io led_segment_bus[4] T5
set_io led_segment_bus[3] T6
set_io led_segment_bus[2] T7
set_io led_segment_bus[1] P8
set_io led_segment_bus[0] T10
set_io led_digit_select[3] T2
set_io led_digit_select[2] T3
set_io led_digit_select[1] R4
set_io led_digit_select[0] R5
# Serial interface
set_io serial_input B10
set_io serial_output B12
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